Such methods are known. With the end of CMOS scaling on the horizon, integrated circuit (IC) manufacturers are looking for alternative ways to boost device density (per foot-print area) and performance. One attractive manner is to build a 3-dimensional IC, in which multiple conventional ICs are stacked on top of each other. In order to realize such a 3D-IC, one crucial issue is to make vertical interconnections between the IC's. It is generally agreed that the size and density of vertical interconnections between devices layers of a 3D IC are of importance to the performance of the IC. Small diameter and high-density vertical interconnections are preferred as they provide more routing freedom in 3D-IC while consuming less active silicon area. Vertical interconnections are usually in the form of through silicon substrate vias.
Nowadays, through substrate (e.g. silicon (Si) substrate) vias are commonly formed by means of dry etching. A fundamental limitation of this technique is the proportional relation between via size (diameter) and via depth. The smaller the via diameter (which is required because of technology scaling), the smaller the via depth. Thus, when used in the manufacturing of 3D-IC's, the via depth dictates the substrate thickness and, therefore, the mechanical and handling properties of an IC layer during the stacking process. A thick substrate is strongly preferred as it provides better mechanical integrity and is easier to handle. A substrate is considered “thick” if it is a significant factor thicker than the via diameter. For instance, if the via diameter is 200 nm, a substrate with a thickness of more than 10 μm is generally considered as thick. However, from a wafer handling point-of-view thick usually means a substrate thicker than 100 μm, which enables conventional handling.
A drawback of the known methods is that they do not enable the manufacturing of high-aspect ratio openings in a substrate when the openings are small. Also the known methods do not enable the manufacturing of high-aspect ratio through-substrate vias. For example, the manufacturing of an opening in a substrate having a diameter of only a few hundred nanometers and a depth of more than 50 μm is impossible with the known methods.